The present invention relates generally to integrated circuit devices and their manufacture and, more particularly, to integrated circuit devices and their manufacture involving analysis of circuit integrity.
The semiconductor industry has recently experienced technological advances that have permitted dramatic increases in circuit density and complexity, and equally dramatic decreases in power consumption and package sizes. Present semiconductor technology now permits single-chip microprocessors with many millions of transistors operating at speeds of hundreds of millions of instructions per second to be packaged in relatively small, air-cooled semiconductor device packages. A by-product of such high-density and high functionality has been an increase in the number and complexity of the manufacturing processes, as well as an increase in the difficulty of maintaining adequate levels of quality control in such processes.
As the manufacturing processes for semiconductor devices increase in difficulty, the cost of such devices rises, and methods for analyzing the devices become increasingly important. Not only is it important to ensure that individual chips are functional, it is also important to ensure that batches of chips perform consistently. In addition, the ability to detect a defective manufacturing process early is advantageous in reducing the number of defective devices manufactured.
A particular attribute of semiconductor manufacturing involves testing the integrity of the device circuitry, such as metal interconnects, transistors, and other devices found in integrated circuits. Ensuring the integrity of such devices is important for maintaining proper circuit function, reliability, and longevity. In many applications, access to device circuitry for performing such testing is difficult, and available testing methods are often impractical or otherwise inefficient.
Due to the cost of manufacturing such devices, and o the necessity of maintaining an adequate level of device quality, the semiconductor industry would benefit from a method and apparatus for efficiently analyzing the circuitry in an integrated circuit die.
The present invention is exemplified in a number of implementations and applications, some of which are summarized below. According to an example embodiment, the present invention is directed to a method for analyzing an integrated circuit device wherein a degree of integrity of circuitry in the device is determined as a function of the decay of a magnetic field in the device.
According to another example embodiment, a method for analyzing an integrated circuit device includes using a magnetic field generator to generate a magnetic field in the integrated circuit device. The magnetic field generator is then stopped, a magnetic field imaging system is used, and the decay of the magnetic field is monitored. A degree of circuit integrity is determined via the monitored decay, e.g., by comparing decay image signatures to an expected xe2x80x9cnormxe2x80x9d signature.
According to yet another example embodiment, a system is configured and arranged to analyze an integrated circuit device. The system includes a magnetic field generator for generating a magnetic field into the integrated circuit device. A magnetic field imaging system for imaging the magnetic field is also included. An analyzing system is used for determining a degree of integrity of the integrated circuit via the magnetic field image generated at the magnetic field imaging system.
The above summary of the present invention is not intended to describe each illustrated embodiment or every implementation of the present invention. The figures and detailed description that follow more particularly exemplify these embodiments.